Wafers and advanced packaging

Primer

What this stage is

The leading-edge logic wafers on which accelerators are made, and the advanced packaging that joins a GPU die to its stacks of high-bandwidth memory. One foundry makes every leading AI accelerator, and one packaging technology, CoWoS, has been the tightest link in the chain since 2023.

How it works

Chips are bought by the wafer. A wafer yields a number of dies that depends on die size and defect rate, and the largest AI dies are close to the maximum size a lithography tool can print. After fabrication, the die and its memory stacks are mounted on a silicon interposer in a packaging step whose capacity, measured in wafers per month, has grown in steps as new lines are added. Capacity is allocated, not sold on a spot market: the largest customers reserve it a year or more ahead.

The foundry's capital spending and its statements about packaging capacity are the clearest public signal of how many accelerators can exist next year.

What to watch

Packaging capacity in wafers per month, and its planned additions.
Leading-edge wafer prices and the share of foundry revenue from AI.
Accelerator dies per wafer by generation.
Foundry capital spending and new fab timing, including the US fabs.
Allocation statements: who has reserved what.

How it connects

Wafers per month, times dies per wafer, times yield, is the ceiling on GPUs per month. Each packaged GPU also fixes its memory demand: a set number of HBM stacks per die.

Figures

Metric	Value	Unit	As of	Scope	Confidence	Source	Note
nvidia_data_center_revenue_q2_fy2027	89	USD billion per quarter	2026-07-26	NVIDIA	high	NVIDIA, Form 8-K exhibit: NVIDIA Announces Financial Results for Second Quarter Fiscal 2027 (Aug. 26, 2026)	Data Center segment revenue (compute plus networking) for the fiscal quarter ended July 26, 2026; total company revenue was $96.2 billion, so Data Center was about 93% of sales, and the company guided total revenue of $108.0 billion plus or minus 2% for the next quarter.
nvidia_data_center_revenue_q1_fy2027	75.2	USD billion per quarter	2026-04-26	NVIDIA	high	NVIDIA, Form 8-K exhibit: NVIDIA Announces Financial Results for First Quarter Fiscal 2027 (May 20, 2026)	Data Center segment revenue for the fiscal quarter ended April 26, 2026, the earlier of the two latest quarters; the sequential step to $89.0 billion is 18%.
amd_data_center_revenue_q2_2026	6.7	USD billion per quarter	2026-06-27	AMD	high	AMD, Form 10-Q for the quarter ended June 27, 2026	AMD's Data Center segment includes EPYC server CPUs as well as Instinct GPUs (MI350 series); AMD does not break out GPU revenue in the 10-Q, so this is an upper bound on its data-centre GPU sales and is about 7.5% of NVIDIA's comparable-quarter figure.
tsmc_2026_capex_guidance_high	64	USD billion per year (upper end of US$60-64 billion range)	2026-07-16	TSMC	medium	W.Media, TSMC raises 2026 capital budget to US$64 billion as HPC demand surges (July 16, 2026), quoting CFO Wendell Huang on the Q2 2026 earnings call	Company guidance for full-year 2026 capital spending, raised from the US$52-56 billion range given in January 2026; Q2 2026 capex alone was US$15.50 billion. Medium confidence because the quote is the CFO's words relayed by a trade publication; TSMC's own 2Q26 transcript PDF on tsmc.com could not be opened by the fetch tool.
tsmc_3nm_share_of_wafer_revenue	30	% of wafer revenue	2026-06-30	TSMC	high	TSMC, Form 6-K: TSMC Reports Second Quarter EPS of NT$27.25 (Jul. 16, 2026)	Share of Q2 2026 wafer revenue from the 3-nanometer node, the leading node in volume during 2026; 5nm was 33%, 7nm 11%, and all nodes at 7nm or below 77%. Total Q2 revenue was US$40.20 billion.
tsmc_cowos_capacity_2026_high	140,000	wafers per month	2026-06	TSMC	low	TrendForce news, citing Economic Daily News: TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026 (June 15, 2026)	High end of a reported 120,000-140,000 wafers-per-month estimate of TSMC's own CoWoS (2.5D advanced packaging) capacity in 2026, attributed to institutional investors via a Taiwanese newspaper; TSMC does not publish this number. The same item says OSAT partners add 50,000-60,000, taking industry capacity toward 200,000 wafers per month, and a Sept. 14, 2026 TrendForce item puts end-2026 TSMC CoWoS at roughly 130,000.
cowos_supply_demand_gap_mid_2026	20	% shortfall of CoWoS supply versus demand	2026-06	global	low	TrendForce news, citing Economic Daily News (June 15, 2026)	Reported gap between CoWoS demand and available capacity in mid-2026, expected to narrow to about 10% by end-2026; this is the clearest public signal that packaging rather than wafer fabrication is the binding constraint on AI accelerator output.
tsmc_2nm_wafer_price	30,000	USD per 300 mm wafer	2025-10	TSMC	low	TrendForce news, citing Investor.com supply-chain sources: TSMC 2nm Reportedly Up 10-20%, Far Below Rumored 50% (Oct. 8, 2025)	Reported price of an N2 wafer at launch, versus about $25,000-27,000 for N3 variants; TSMC does not disclose wafer prices and the same item reports single-digit percentage increases for 3-7nm in 2026, so the N3 figure has likely risen slightly since.
b200_sale_price_high	40,000	USD per GPU (upper end of $30,000-40,000 reported range)	2025-12-10	NVIDIA B200	low	Epoch AI, NVIDIA's B200 costs around $6,400 to produce (Dec. 10, 2025)	Reported per-chip sale price for the B200, against Epoch's own estimate that it costs $5,700-7,300 to make (HBM about $2,900, advanced packaging about $1,100, 4NP wafer about $17,000); NVIDIA publishes no list price. A separate OEM-quote page (Northflank, Aug. 2025) put a B200 192GB SXM at $45,000-50,000, and CloudZero (Aug. 24, 2026) listed a new H100 80GB at about $31,000.
gb200_nvl72_rack_price_low	2.8	USD million per GB200 NVL72 rack (low end of reported range)	2026-03-24	NVIDIA GB200 NVL72	low	Tom's Hardware via Yahoo Finance, Price of Nvidia's Vera Rubin NVL72 racks skyrockets to as much as $8.8 million apiece (Mar. 24, 2026)	As printed: 2.8 USD million per 72-GPU rack (low end of $2.8-3.4 million range). Price of a GB200 NVL72 rack according to a source with knowledge of the matter, not an NVIDIA list price; the same article gives $6-6.5 million for a GB300 NVL72 and $5-7 million for a Vera Rubin VR200 NVL72, and a Barron's writer put GB200 NVL72 at about $3 million. Dividing $2.8 million by 72 GPUs gives about $39,000 per GPU slot, all-in.
bis_china_case_by_case_tpp_threshold	21,000	TPP (total processing performance), upper bound for case-by-case licensing to China and Macau	2026-01-15	US	high	Bureau of Industry and Security, Revision to License Review Policy for Advanced Computing Commodities, 91 FR 1684 (effective Jan. 15, 2026)	The rule that governs China sales today: chips with TPP below 21,000 and total DRAM bandwidth below 6,500 GB/s (the NVIDIA H200 and AMD MI325X class) moved from presumption of denial to case-by-case review, subject to conditions including US third-party testing and a cap that shipments to China and Macau be no more than 50% of the volume shipped for US end use; Blackwell-class parts remain above the threshold, and NVIDIA still assumes no China Data Center compute revenue in its outlook.
nvidia_extended_lead_time_experienced	12	months (lower bound of extended supply lead times NVIDIA says it has experienced)	2026-01-25	NVIDIA	high	NVIDIA, Form 10-K for the fiscal year ended January 25, 2026	The only company-stated lead-time figure found: NVIDIA's risk-factor disclosure that supply lead times have exceeded 12 months, which is why it builds inventory ahead of demand and prepays for capacity; the 10-K also says it uses TSMC and Samsung foundries. NVIDIA's supply and capacity commitments rose from $119 billion to $279 billion in the quarter ended July 26, 2026, primarily for memory (CFO commentary).

Conversions

From → To	Factor	Unit	As of	Confidence	Source	Note
Memory and storage (HBM, DRAM, NAND) → Wafers and advanced packaging	3	DRAM wafers consumed per bit, HBM3E relative to DDR5 at the same node (ratio)	2026-08-23	medium	MLQ News report of Micron's Hot Chips 2026 presentation (Raghu Sreeramaneni, Micron), Aug 26, 2026	Micron's 'trade ratio': each HBM bit removes about three DDR5 bits of wafer capacity, and Micron said the HBM4 ratio is higher. Secondary report of a company presentation; Micron's own remarks PDFs redirect.
Wafers and advanced packaging → GPUs, servers, racks and networking	3,958	teraFLOPS FP8 Tensor Core per GPU, with sparsity (H100 SXM)	2026-09	high	NVIDIA, H100 Tensor Core GPU product page, specifications table	Hopper-generation peak FP8 throughput per GPU as listed in the datasheet table; the figure is 'with sparsity', so dense FP8 is half (1,979 teraFLOPS), and FP16/BF16 with sparsity is 1,979 teraFLOPS. The quote is a table cell, hence shorter than eight words.
Wafers and advanced packaging → GPUs, servers, racks and networking	9	petaFLOPS FP8 Tensor Core per GPU, with sparsity (B200, from 72 PFLOPS per 8-GPU DGX B200)	2026-09	high	NVIDIA, DGX B200 product page, specifications table	Arithmetic: DGX B200 lists FP8 Tensor Core 72 PFLOPS for 8 Blackwell GPUs, so 72 / 8 = 9 PFLOPS per B200, about 2.3x the H100's 3.958 PFLOPS; the GB200 NVL72 page lists FP4 1,440 PFLOPS for 72 GPUs, i.e. 20 PFLOPS FP4 per GB200 GPU. The quote is a table cell.
Wafers and advanced packaging → Power generation and fuel	0.7	kW per GPU, chip TDP only (H100 SXM)	2026-09	high	NVIDIA, H100 Tensor Core GPU product page, specifications table	Arithmetic: 700 W = 0.7 kW; this is the GPU module's maximum thermal design power alone, before CPUs, networking, fans and cooling overhead. The PCIe/NVL variant is 350-400 W.
Wafers and advanced packaging → Power generation and fuel	1.2	kW per GPU, chip TDP only (Blackwell GPU in the GB200 superchip)	2024-03-22	medium	Wccftech, NVIDIA's Fully-Enabled Blackwell B200 GPUs Consume Up To 1200W (Mar. 22, 2024), reporting NVIDIA GTC 2024 sessions	Arithmetic: 1,200 W = 1.2 kW for the full-spec Blackwell GPU used in GB200; the same report says the HGX/DGX B200 variant 'is optimized around 1000W' (1.0 kW) and B100 at 700 W. NVIDIA's own GB200 NVL72 page lists no power figure, so this is a press report of NVIDIA engineers' statements rather than a datasheet.
Wafers and advanced packaging → Data centre shell and cooling	1.79	kW per GPU, all-in at the server level (DGX B200, 8 GPUs)	2026-09	high	NVIDIA, DGX B200 product page, specifications table	Arithmetic: the 8-GPU DGX B200 system draws about 14.3 kW maximum, so 14.3 / 8 = 1.79 kW per GPU including the two host CPUs, NICs, fans and power-supply losses; this is the number to use for IT load per GPU in an air-cooled Blackwell server, versus about 1.0 kW for the GPU chip alone.
Wafers and advanced packaging → Data centre shell and cooling	120	kW of IT load per GB200 NVL72 rack (72 GPUs), liquid-cooled	2024-07-17	medium	SemiAnalysis, GB200 Hardware Architecture - Component Supply Chain & BOM (July 17, 2024), free section	Rack-level power for the 72-GPU NVL72 (18 compute trays at a 6.3 kW max TDP each plus NVLink switch trays); arithmetic: 120 / 72 = 1.67 kW per GPU all-in, and a hosting provider (Pantheon, Aug. 2026) says NVIDIA's rack guide lists approximately 120 kW for GB200 NVL72 and up to 142 kW for GB300 NVL72. Requires direct liquid cooling; typical air-cooled H100 racks were about 40 kW.
Wafers and advanced packaging → GPUs, servers, racks and networking	72	GPUs per rack (GB200 NVL72)	2026-09	high	NVIDIA, GB200 NVL72 product page, specifications table	One NVL72 rack holds 36 Grace CPUs and 72 Blackwell GPUs in a single NVLink domain; the same table lists 13.4 TB of HBM3E per rack, i.e. 13,400 / 72 = 186 GB of HBM per GPU (or 372 GB per two-GPU superchip), which is the bridge to the memory stage.
Wafers and advanced packaging → GPUs, servers, racks and networking	25	gross CoWoS interposers (GPU packages) per 300 mm wafer, before yield (low end of 25-28)	2026-04-13	low	Silicon Analysts, CoWoS Cost 2026: $750-1,100/Chip, Chiplet vs Monolithic (Apr. 13, 2026)	Analyst-site estimate with no primary citation, for a B200-class package (two near-reticle dies plus eight HBM stacks); applying its 60-70% interposer yield gives about 15-19 good packages per CoWoS wafer, so 130,000 wafers per month would be roughly 2-2.5 million such GPUs per month. TSMC does not publish packages per wafer; treat as an order-of-magnitude figure.

Players

Company	Ticker	Role	Listed	Note
NVIDIA	NASDAQ:NVDA	GPU and rack-scale system design (fabless)	yes	Data Center revenue of $89.0 billion in the quarter ended July 26, 2026, up 117% year on year, with the Blackwell architecture 'the vast majority' of revenue and supply commitments of $279 billion; it buys wafers from TSMC and packaging on CoWoS.
AMD	NASDAQ:AMD	GPU (Instinct) and server CPU (EPYC) design (fabless)	yes	The only merchant GPU alternative at scale: Data Center segment revenue $6.7 billion in the quarter ended June 27, 2026, up 107%, driven by EPYC CPUs and Instinct MI350 GPUs; also fabs at TSMC.
Broadcom	NASDAQ:AVGO	Custom AI ASIC (XPU) design for hyperscalers plus Ethernet networking silicon	yes	Largest custom-accelerator designer (Google TPU and other hyperscaler programs): AI semiconductor revenue of $16.7 billion in the quarter ended Aug. 2, 2026, up 221% year on year, with $21.7 billion guided for the next quarter.
Marvell Technology	NASDAQ:MRVL	Custom AI ASIC design and data-centre connectivity silicon	yes	Second custom-silicon house for hyperscalers: quarterly revenue $2.739 billion in the quarter ended Aug. 1, 2026 with data-centre revenue up 46% year on year, and a custom-chip ramp it says begins in the second half of fiscal 2027.
TSMC	NYSE:TSM (ADR); TWSE:2330	Leading-edge foundry (N3, N2) and CoWoS advanced packaging	yes	Makes essentially every AI accelerator in volume: Q2 2026 revenue US$40.20 billion with 3nm at 30% of wafer revenue, 2026 capex guided to US$60-64 billion, and reported CoWoS capacity of 120,000-140,000 wafers per month in 2026.
Samsung Foundry (Samsung Electronics)	KRX:005930	Second-source leading-edge foundry (2nm) with a US fab	yes	The only other foundry shipping sub-3nm logic; its largest foundry win is a $16.5 billion Tesla AI6 contract running to end-2033 on its 2nm process at Taylor, Texas, and NVIDIA's 10-K names it alongside TSMC as a wafer supplier.
Intel Foundry (Intel)	NASDAQ:INTC	US-based foundry (18A in volume, 14A in development) and advanced packaging (EMIB, Foveros)	yes	The would-be third leading-edge foundry: Intel Foundry revenue $5.8 billion in Q2 2026 (up 31%, mostly internal) with an operating loss of $2,089 million; 18A is in high-volume manufacturing for Panther Lake and 18A-P entered risk production, but external AI-accelerator volume is not yet proven.
ASML	NASDAQ:ASML; AMS:ASML	Sole supplier of EUV lithography tools that every leading-edge fab needs	yes	Gates how fast N3/N2/18A capacity can be added: Q2 2026 net sales EUR 9.3 billion, 2026 low-NA EUV capacity of around 65 systems with a 30% addition planned for 2027, and 2026 sales guided to EUR 43-45 billion.
Alchip Technologies	TWSE:3661	Custom ASIC design services (TSMC ecosystem) for hyperscaler accelerators	yes	Design-services partner behind AWS's Trainium 3: the 3nm chip was reported to enter mass production in Q2 2026, and Alchip says several 2nm AI and HPC projects are under way.
Global Unichip (GUC)	TWSE:3443	Custom ASIC design services and turnkey manufacturing; TSMC affiliate	yes	TSMC's in-house-adjacent design house for custom silicon (HBM and UCIe IP, advanced packaging); reported to have secured next-generation CPU projects from Google and Meta, and ASIC-based servers are forecast at 27.8% of AI server shipments in 2026.
Cerebras Systems	NASDAQ:CBRS	Wafer-scale AI accelerator design (WSE-3) and inference cloud	yes	The main non-GPU, non-ASIC architecture at scale: 2025 revenue of about $510 million (S-1 table: 509,991 in thousands, versus 290,252 in 2024) and a multi-year OpenAI deal worth more than $20 billion for 750 MW of compute; its WSE-3 is a single chip '58 times larger than NVIDIA's B200'.
Groq	private	LPU inference accelerator design	no	Inference-specialist chip designer whose technology NVIDIA agreed in December 2025 to license for nearly $20 billion while hiring CEO Jonathan Ross and senior engineers; the deal has since drawn antitrust scrutiny (Bloomberg, Sept. 2026, paywalled).